SOC DFT Engineer

1.Responsible for SOC chip-level and sub-system level DFT architecture definition, scan insertion, scan timing constraint, ATPG pattern generation/simulation, ATPG post-silicon diagnosis, MP support and etc. 2.Support chip-level/sub-system DFT related check and implementation, including ATPG DRC, ATPG coverage improve, ATPG pattern count reduction, Equivalence check, Scan SDC constraint, Timing Si…… 完整岗位描述与官方投递入口,请登录后在岗位详情页查看。