Lead Design Engineer(Virtual Solution)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium) Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation Develop end-to-end verification flows including: AVIP integrati…… 完整岗位描述与官方投递入口,请登录后在岗位详情页查看。