岗位描述（节选）
The candidate is expected to be responsible for following tasks:
- Participate in complex Chip DFT/DFD feature and architecture definition
- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work for timing closure
- Develop and verify high coverage and cost effective test patterns for the production test
- Design, im……
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